1. Field of the Invention
The invention relates to an absolute value detecting circuit and a system for detecting an amplitude value of a certain signal, namely, an absolute value of the signal for a predetermined potential and, more particularly, to a signal processing circuit and a system for detection of an absolute value each of which is constructed by combining an emitter coupling circuit of a transistor and an inverting amplifier.
2. Related Background Art
In the electric and electronic fields, in the case where an input signal has amplitudes in both of the positive and negative directions in terms of a voltage for a predetermined voltage level (reference voltage level) (in the case where it has amplitudes in an AC manner), a circuit to detect a difference between the level of the input signal and the reference voltage level is called an absolute value detecting circuit. As a construction of such an absolute value detecting circuit, for instance, there is a construction as shown in FIG. 1. In FIG. 1, reference numeral 18 denotes a voltage clamp circuit to fix an operating voltage level in the circuit to a proper voltage value irrespective of the voltage level of an AC input signal which is supplied from V.sub.IN. Reference numerals 11 and 12 denote inverting amplifiers each of which comprises a resistor R, a reference voltage V.sub.R, and an operational amplifier and 16 indicates an absolute value detecting circuit comprising an emitter coupling circuit of NPN transistors 13 and 14 and a constant current circuit 15.
Generally, in the case where a signal voltage which is applied to the input V.sub.IN is an AC input signal at various levels, a method of first passing the AC input signal through the clamp circuit in order to set the AC input signal to a signal so as to have an amplitude with a predetermined voltage as a reference. After the AC input signal was adjusted to a proper operating level by the clamp circuit, it passes through a signal processing circuit for detection of the absolute value which is constructed by the inverting amplifier and the emitter coupling circuit and is generated from an output terminal V.sub.out. FIG. 2 shows a voltage level at each point in the circuit of FIG. 1. In FIG. 2, a voltage level V.sub.l of V.sub.IN is an arbitrary voltage and it is assumed that the voltage level V.sub.1 can have any value in accordance with a state of an original input signal (a). The potential of V.sub.l is fixed to a proper level by the subsequent clamp circuit and sent to the inverting amplifier. In the circuit of FIG. 1, although a gain of the inverting amplifier is set to an equal magnification ratio as shown in FIG. 2, such a gain can be arbitrarily set. Now, assuming that an output point at which the signal has passed through the inverting amplifier once is set to A and an output point at which the signal has passed through the inverting amplifier twice is set to B, output waveforms at A and B points are as shown in (b) in FIG. 2. Although output amplitudes can be set to any values in accordance with the gain of the inverting amplifier, all of the output voltage levels are fixed to the reference voltage V.sub.R.
After that, a waveform appearing at the final output terminal V.sub.out by passing the signal through the absolute value detecting circuit 16 which couples the emitters of the NPN transistors is as shown in (c) in FIG. 2. The voltage level of the output in this instance is generated as levels, that is, V.sub.R -V.sub.BE(13,14) which are lower than V.sub.R by only the values of base-emitter voltages V.sub.BE(13) and V.sub.BE(14) of the NPN transistors 13 and 14 for V.sub.R.
FIG. 3 is a circuit diagram of each of the inverting amplifiers 11 and 12 in FIG. 1.
As results of many experiments executed repeatedly by the inventors of the present invention, however, it has been found out that a difference occurs between the output voltage of the inverting amplifier and the output voltage of the absolute value detecting circuit in the above conventional apparatus. Practically speaking, there occurs a phenomenon such that the operating point (operating voltage) is shifted to lower values by only the base-emitter voltages V.sub.BE(13) and V.sub.BE(14) of the NPN transistors 13 and 14.
Hitherto, since such a circuit has been examined from only a viewpoint of the AC operation, it is considered that the above problem cannot be found out.
The present inventors have found out the above problem when they tried to apply such a circuit to a circuit which handles the voltage level of the output signal in a DC manner.
That is, in the circuit which handles the output voltage level in a DC manner, there is a possibility of the occurrence of inconveniences such as fluctuation of the operating point and decrease in dynamic range. It is considered that the voltages V.sub.BE(13) and V.sub.BE(14) change in dependence on a value of current I flowing in the constant current circuit 15 and differences of the characteristics of respective transistors. For instance, when such a circuit is intended to be realized by a semiconductor integrated circuit, this results in a cause of occurrence of a large fluctuation in the output voltage level due to a variation in sizes of transistors, a variation in resistance values, differences of the temperature characteristics of the respective devices, and the like.